#ifndef T1_SYSCTL_H_
#define T1_SYSCTL_H_

#include "iodef.h"

typedef struct {
        __IO uint32_t SYS_OSC;                  /* OSC control and system reset */
        __IO uint32_t INT_EN;                   /* Interrupt Enable */
        __IO uint32_t INT_CLR;                  /* Interrupt Clear */
        __IO uint32_t INT_STA;                  /* Interrupt Status */
        __IO uint32_t PLL_CFG;                  /* PLL Configuration */
        __IO uint32_t CLK_SWT;                  /* Clock Switch Control */
        __IO uint32_t Reserved0[2];
        __IO uint32_t CLK_DIV0;                 /* Clock Divide Control Register 0 */
        __IO uint32_t CLK_DIV1;                 /* Clock Divide Control Register 1 */
        __IO uint32_t CLK_DIV2;                 /* Clock Divide Control Register 2 */
        __IO uint32_t CLK_DIV3;                 /* Clock Divide Control Register 3 */
        __IO uint32_t CLK_GATE0;                /* Clock Gating Control Register 0 */
        __IO uint32_t CLK_GATE1;                /* Clock Gating Control Register 1 */
        __IO uint32_t CLK_DIV4;                 /* Clock Divide Control Register 4 */
        __IO uint32_t CLK_DIV5;                 /* Clock Divide Control Register 5 */
        __IO uint32_t RST_SOFT0;                /* Soft Reset Register 0 */
        __IO uint32_t RST_SOFT1;                /* Soft Reset Register 1 */
        __IO uint32_t Reserved1[2];
        __IO uint32_t SYS_STA;                  /* System Status */
        __IO uint32_t Reserved2[43];
        __IO uint32_t RNG_CTL;                  /* RNG Control Register */
        __IO uint32_t RNG_VAL;                  /* RNG Value Register */
        __IO uint32_t Reserved3[2];
        __IO uint32_t AESKEY_CTL;               /* AES Key Control Register */
        __IO uint32_t Reserved4[3];
        __IO uint32_t AESKEY_D[4];              /* AES Key Data */
        __IO uint32_t Reserved5[4];
        __IO uint32_t EFUSE_CTL;                /* eFuse Control Register */
        __IO uint32_t Reserved6[3];
        __IO uint32_t XSRAM_CTL;                /* EMI SRAM XOR Control */
        __IO uint32_t XSRAM_KEY;                /* EMI SRAM XOR Key Data */
        __IO uint32_t Reserved7[2];
        __IO uint32_t SMC_TIM;                  /* Static memory timing (EMI) */
        __IO uint32_t FLASH_TRPDR;              /* FLASH Trpd timing (EMI) */
        __IO uint32_t SMC_CTL;                  /* Static Memory Control (EMI) */
        __IO uint32_t Reserved8[101];
        __IO uint32_t SRAM_MODE;                /* SRAM mode selection */
        __IO uint32_t ISO_CTL;                  /* ISO Control Register */
        __IO uint32_t ISO_RST_W;                /* ISO0/ISO1 Reset Width */
        __IO uint32_t ISO_RST_W2;               /* ISO2 Reset Width */
        __IO uint32_t Reserved9[60];
        __IO uint32_t SVDT_CFG;                 /* SVDT Configuration */
        __IO uint32_t RCG_CFG;                  /* RCG Configuration */
        __IO uint32_t Reserved10[2];
        __IO uint32_t PIN_MUXING0;              /* PIN Muxing Configuration 0 */
        __IO uint32_t Reserved11[3];
        __IO uint32_t PIN_MUXING1;              /* PIN Muxing Configuration 1 */
}syscfg_reg_t;

/* SYS_OSC */
#define MOSC_EN          _BIT(31)               /* Enable the MOSC(24MHz) pad */
#define OSC_SWT_SOFT     _BIT(29)               /* CLK_SWT decides the system clock */
#define MOSC_TST_EN      _BIT(24)               /* MOSC(24MHz) clock test enable */
#define SOFT_RESET_MSK   _MASK(0, 16)
#define SOFT_RESET_VAL   _VALUE(0, 0x55AA)      /* Soft reset for the whole system */

/* INT_EN & INT_CLR & INT_STA */
#define SYSCFG_INT       _BIT(31)               /* Interrupt for system configuration */
#define ICC_IN_INT       _BIT(0)                /* Interrupt for ICC insertion in ISO 0 */

/* PLL_CFG: FCLK = (FOSC / M) x N */
#define PLL_PWD          _BIT(31)               /* PLL Power Down */
#define PLL_DN_MSK       _MASK(16, 7)
#define PLL_DN(dn)       _VALUE(16, (dn - 1))       /* N = DN[6:0] + 1 */
#define PLL_DM_MSK       _MASK(0, 5)
#define PLL_DM(dm)       _VALUE(0, (dm - 1))        /* M = DM[4:0] + 1 */

/* CLK_SWT */
#define FOSC_CLK_MOSC    _BIT(16)
#define WDT_CLK_MOSC     _BIT(7)
#define ADC_CLK_PLL      _BIT(6)
#define DEF_CLK_PLL      _BIT(5)
#define RAN_CLK_PLL      _BIT(4)
#define FSK_CLK_PLL      _BIT(3)
#define ISO_CLK_PLL      _BIT(2)
#define CRYPTO_CLK_PLL   _BIT(1)
#define AHB_CLK_PLL      _BIT(0)

/* CLK_DIV0 */
#define FSK_DIV_MSK      _MASK(18, 14)
#define FSK_DIV(n)       _VALUE(18, (n - 1))
#define PCLK1_DIV_MSK    _MASK(12, 6)
#define PCLK1_DIV(n)     _VALUE(12, (n - 1))
#define PCLK0_DIV_MSK    _MASK(6, 6)
#define PCLK0_DIV(n)     _VALUE(6, (n - 1))
#define HCLK_DIV_MSK     _MASK(0, 6)
#define HCLK_DIV(n)      _VALUE(0, (n - 1))

/* CLK_DIV1 */
#define RAN_DIV_MSK      _MASK(28, 4)
#define RAN_DIV(n)       _VALUE(28, (n - 1))
#define ADC_DIV_MSK      _MASK(16, 6)
#define ADC_DIV(n)       _VALUE(16, (n - 1))
#define OUTCLK_DIV_MSK   _MASK(6, 6)
#define OUTCLK_DIV(n)    _VALUE(6, (n - 1))
#define UART0_DIV_MSK    _MASK(0, 6)
#define UART0_DIV(n)     _VALUE(0, (n - 1))

/* CLK_DIV2 */
#define ISO2_DIV_MSK     _MASK(18, 9)
#define ISO2_DIV(n)      _VALUE(18, (n - 1))
#define ISO1_DIV_MSK     _MASK(9, 9)
#define ISO1_DIV(n)      _VALUE(9, (n - 1))
#define ISO0_DIV_MSK     _MASK(0, 9)
#define ISO0_DIV(n)      _VALUE(0, (n - 1))

/* CLK_DIV3 */
#define WDT_DIV_MSK      _MASK(18, 10)
#define WDT_DIV(n)       _VALUE(18, (n - 1))
#define DEF_DIV_MSK      _MASK(12, 6)
#define DEF_DIV(n)       _VALUE(12, (n - 1))
#define USB_DIV_MSK		 _MASK(6, 6)
#define USB_DIV(n)		 _VALUE(6, (n -  1))
#define CRYPTO_DIV_MSK   _MASK(0, 6)
#define CRYPTO_DIV(n)    _VALUE(0, (n - 1))

/* CLK_DIV4 */
#define TIM4_DIV_MSK     _MASK(24, 8)
#define TIM4_DIV(n)      _VALUE(24, (n - 1))
#define TIM3_DIV_MSK     _MASK(16, 8)
#define TIM3_DIV(n)      _VALUE(16, (n - 1))
#define TIM2_DIV_MSK     _MASK(8, 8)
#define TIM2_DIV(n)      _VALUE(8, (n - 1))
#define TIM1_DIV_MSK     _MASK(0, 8)
#define TIM1_DIV(n)      _VALUE(0, (n - 1))

/* CLK_DIV5 */
#define TIM0_DIV_MSK     _MASK(8, 6)
#define TIM0_DIV(n)      _VALUE(8, (n - 1))
#define TIM5_DIV_MSK     _MASK(0, 8)
#define TIM5_DIV(n)      _VALUE(0, (n - 1))

/* CLK_GATE0 */
#define PCLK1_CLK_EN     _BIT(31)
#define PCLK0_EN         _BIT(30)
#define SPI1_CLK_EN      _BIT(29)
#define SPI0_CLK_EN      _BIT(28)
#define FSK_CLK_EN       _BIT(27)
#define MAG_CLK_EN       _BIT(26)
#define ISO2_CLK_EN      _BIT(25)
#define ISO1_CLK_EN      _BIT(24)
#define ISO0_CLK_EN      _BIT(23)
#define RTC_CLK_EN       _BIT(22)
#define DEF_CLK_EN       _BIT(21)
#define SYSCFG_CLK_EN    _BIT(20)
#define DAC_CLK_EN       _BIT(19)
#define PWM_CLK_EN       _BIT(18)
#define WDT_CLK_EN       _BIT(17)
#define TIM_CLK_EN       _BIT(16)
#define GPIO_CLK_EN      _BIT(15)
#define ICTL_CLK_EN      _BIT(14)
#define UART3_CLK_EN     _BIT(13)
#define UART2_CLK_EN     _BIT(12)
#define UART1_CLK_EN     _BIT(11)
#define UART0_CLK_EN     _BIT(10)
#define BUS_CLK_EN       _BIT(9)
#define EMI_CLK_EN       _BIT(6)
#define CRYPTO_CLK_EN    _BIT(5)
#define DROM_CLK_EN      _BIT(3)
#define SRAM_CLK_EN      _BIT(2)
#define EFLASH_CLK_EN    _BIT(1)
#define MIPS_CLK_EN      _BIT(0)

/* CLK_GATE1 */
#define TIM5_CLK_EN      _BIT(31)
#define TIM4_CLK_EN      _BIT(30)
#define TIM3_CLK_EN      _BIT(29)
#define TIM2_CLK_EN      _BIT(28)
#define TIM1_CLK_EN      _BIT(27)
#define NCS_CLK_EN       _BIT(26)
#define RCG_CLK_EN       _BIT(25)
#define RNG_CLK_EN       _BIT(24)
#define SYSCFG_CLK2_EN   _BIT(20)
#define DEF_CLK2_EN      _BIT(19)
#define USB_CLK_EN		 _BIT(18)
#define WDT_CLK2_EN      _BIT(17)
#define ADC_CLK_EN      _BIT(16)
#define FSK_CLK2_EN      _BIT(12)
#define UART0_CLK2_EN    _BIT(11)
#define TIM0_CLK_EN      _BIT(10)

/*
 * The below ISO clock gates function the same as in the ISO_CTL
 */
#define _ISO2_TX_CLK_EN   _BIT(9)
#define _ISO1_TX_CLK_EN   _BIT(8)
#define _ISO0_TX_CLK_EN   _BIT(7)
#define _ISO2_RX_CLK_EN   _BIT(6)
#define _ISO1_RX_CLK_EN   _BIT(6)
#define _ISO0_RX_CLK_EN   _BIT(6)

#define CRYPTO_CLK2_EN   _BIT(0)

/* SOFT_RST0 */
#define ISO2_EX_RST      _BIT(29)
#define ISO1_EX_RST      _BIT(28)
#define ISO0_EX_RST      _BIT(27)
#define ISO2_RST         _BIT(26)
#define ISO1_RST         _BIT(25)
#define ISO0_RST         _BIT(24)
#define UART0_RST        _BIT(19)
#define FSK_RST          _BIT(18)
#define TIM0_RST         _BIT(17)
#define RAN_RST          _BIT(16)
#define CRYPTO_RST       _BIT(15)
#define EMI_HRST         _BIT(6)
#define CRYPTO_HRST      _BIT(5)
#define DROM_HRST        _BIT(3)
#define SRAM_HRST        _BIT(2)
#define EFLASH_HRST      _BIT(1)

/* SOFT_RST1 */
#define SPI1_PRST        _BIT(24)
#define SPI0_PRST        _BIT(23)
#define FSK_PRST         _BIT(22)
#define MAG_PRST         _BIT(21)
#define ISO2_PRST        _BIT(20)
#define ISO1_PRST        _BIT(19)
#define ISO0_PRST        _BIT(18)
#define RTC_PRST         _BIT(17)
#define DEF_PRST         _BIT(16)
#define DAC_PRST         _BIT(9)
#define PWM_PRST         _BIT(8)
#define WDT_PRST         _BIT(7)
#define TIM_PRST         _BIT(6)
#define GPIO_PRST        _BIT(5)
#define ICTL_PRST        _BIT(4)
#define UART3_PRST       _BIT(3)
#define UART2_PRST       _BIT(2)
#define UART1_PRST       _BIT(1)
#define UART0_PRST       _BIT(0)

/* SYS_STA */
#define OSC_USE_ROSC     _BIT(4)        /* GPIO104 decides the OSC selected */

/* RNG_CTL */
#define RNG_EN           _BIT(0)

/* AESKEY_CTL */
#define KEY_RW_DIS       _BIT(12)       /* AES Key data Read/Write disable */
#define KEY_SEL_SYS      _BIT(8)        /* AES key from AESKEY_Dn */
#define EMI_KEY_KLD      _BIT(4)        /* Load the key to the EMI AES module */
#define EMI_AES_EN       _BIT(0)        /* Enable the AES feature in EMI */

/* EFUSE_CTL */
#define EFUSE1_BURN_EN   _BIT(31)
#define EFUSE0_BURN_EN   _BIT(24)
#define EFUSE1_VAL       _BIT(12)
#define EFUSE1_SWD_DIS   _BIT(8)        /* Shadow bit disable */
#define EFUSE0_VAL       _BIT(4)
#define EFUSE0_SWD_DIS   _BIT(0)        /* Shadow bit disable */

/* SRAM_CTL */
#define XOR_RW_DIS       _BIT(4)        /* SRAM XOR Key Read/Write Disable */
#define XOR_STEP_EN      _BIT(0)        /* Enable XOR step for SRAM data IN/OUT */

/* SMC_TIM */
#define T_BRC_MSK        _MASK(19, 6)
#define T_BRC(n)         _VALUE(19, (n))
#define T_BTA_MSK        _MASK(16, 3)
#define T_BTA(n)         _VALUE(16, (n))
#define T_WP_MSK         _MASK(10, 6)
#define T_WP(n)          _VALUE(10, (n))
#define T_WR_MSK         _MASK(8, 2)
#define T_WR(n)          _VALUE(8, (n))
#define T_AS_MSK         _MASK(6, 2)
#define T_AS(n)          _VALUE(6, (n))
#define T_RC_MSK         _MASK(0, 6)
#define T_RC(n)          _VALUE(0, (n))

/* FLASH_TRPDR */
#define T_RPD_MSK        _MASK(0, 12)
#define T_RPD(n)         _VALUE(0, (n))

/* SMC_CTL */
#define SMC_WP_N         _BIT(1)
#define SMC_RP_N         _BIT(0)

/* SRAM_MODE */
#define EMI_SEL_EX       _BIT(8)
#define EX_SRAM_8BIT     _BIT(4)

/* SVDT_CFG */
#define SVDT_RST_EN      _BIT(16)
#define SVDT33_L         _BIT(7)
#define SVDT33_H         _BIT(6)
#define SVDT18_L         _BIT(5)
#define SVDT18_H         _BIT(4)
#define SVDT_FILTER      _BIT(1)
#define SVDT_EN          _BIT(0)

/* RCG_CFG */
#define NCS_ISET_MSK     _MASK(8, 3)
#define NCS_ISET(n)      _VALUE(8, n)
#define NCS_EN           _BIT(4)
#define RCG_EN           _BIT(0)

/* PIN_MUXING0 */
#define GPIO76_EN        _BIT(22)
#define GPIO78_79_80_EN  _BIT(21)
#define GPIO73_74_75_EN  _BIT(20)
#define GPIO60_EN        _BIT(19)
#define GPIO59_EN        _BIT(17)
#define GPIO58_EN        _BIT(13)
#define GPIO54_EN        _BIT(11)
#define GPIO53_EN        _BIT(10)
#define GPIO52_EN        _BIT(9)
#define GPIO51_EN        _BIT(8)
#define GPIO32_EN        _BIT(7)
#define GPIO31_EN        _BIT(5)
#define GPIO11_EN        _BIT(4)
#define GPIO33_55_EN     _BIT(3)
#define GPIO42_TO_49_EN  _BIT(1)
#define EMI_PIN_DIS      _BIT(0)

/* PIN_MUXING1 */
#define GPIO94_FUNC_MSK  _MASK(29, 2)
#define GPIO94_EN        _VALUE(29, 0x2)
#define PWM2_PIN_EN      _VALUE(29, 0x1)
#define ISO2_CLK_PIN_EN  _VALUE(29, 0x0)

#define GPIO91_FUNC_MSK  _MASK(27, 2)
#define GPIO91_EN        _VALUE(27, 0x2)
#define PWM2_PIN2_EN     _VALUE(27, 0x1)
#define ISO1_CLK_PIN_EN  _VALUE(27, 0x0)

#define GPIO90_92_93_95_EN      _BIT(26)

#define GPIO125_FUNC_MSK        _MASK(24, 2)
#define GPIO125_EN              _VALUE(24, 0x2)
#define PWM3_PIN_EN             _VALUE(24, 0x1)
#define ISO0_CLK_PIN_EN         _VALUE(24, 0x0)

#define GPIO123_124_126_EN      _BIT(18)
#define GPIO112_EN              _BIT(17)
#define GPIO113_TO_122_EN       _BIT(16)
#define GPIO85_TO_89_EN         _BIT(15)
#define GPIO84_DIS              _BIT(14)
#define PWM1_PIN_EN             GPIO84_DIS
#define GPIO83_DIS              _BIT(13)
#define GPIO71_72_DIS           _BIT(12)

#define GPIO69_70_FUNC_MSK      _MASK(10, 2)
#define GPIO69_70_EN            _VALUE(10, 0x2)
#define TXD3_RXD3_PIN_EN        _VALUE(10, 0x1)
#define nRTS1_nCTS1_PIN_EN      _VALUE(10, 0x0)

#define GPIO67_68_FUNC_MSK      _MASK(8, 2)
#define GPIO67_68_EN            _VALUE(8, 0x2)
#define nRTS2_nCTS2_PIN_EN      _VALUE(8, 0x1)
#define RING_DCD_PIN_EN         _VALUE(8, 0x0)

#define GPIO65_66_FUNC_MSK      _MASK(6, 2)
#define GPIO65_66_EN            _VALUE(6, 0x2)
#define TXD2_RXD2_PIN_EN        _VALUE(6, 0x1)
#define nDTR_nDSR_PIN_EN        _VALUE(6, 0x0)

#define GPIO63_64_FUNC_MSK      _MASK(4, 2)
#define GPIO63_64_EN            _VALUE(4, 0x2)
#define SIR_TX_RX_PIN_EN        _VALUE(4, 0x1)
#define TXD0_RXD0_EN            _VALUE(4, 0x0)

#define GPIO61_62_EN            _BIT(3)
#define GPIO82_EN               _BIT(2)
#define GPIO81_EN               _BIT(1)
#define GPIO77_EN               _BIT(0)

/* ISO_CTL */
#define ISO2_IO_MOD             _BIT(23)
#define ISO2_IO_DATA            _BIT(22)
#define ISO1_IO_MOD             _BIT(21)
#define ISO1_IO_DATA            _BIT(20)
#define ISO0_M_IO_ES_MSK        _MASK(17, 3)
#define ISO0_M_IO_ES(n)         _VALUE(17, (n))
#define ISO0_M_IO_5V            _BIT(16)
#define ISO0_NOCARD             _BIT(13)
#define ISO0_VCC_5V             _BIT(12)
#define ISO0_VCC_3V             _BIT(11)
#define ISO0_VCC_EN             _BIT(10)
#define ISO2_VCC_EN             _BIT(9)
#define ISO1_VCC_EN             _BIT(8)
#define HW_PD_EN                _BIT(6)
#define ISO2_RX_CLK_EN          _BIT(5)
#define ISO1_RX_CLK_EN          _BIT(4)
#define ISO0_RX_CLK_EN          _BIT(3)
#define ISO2_TX_CLK_EN          _BIT(2)
#define ISO1_TX_CLK_EN          _BIT(1)
#define ISO0_TX_CLK_EN          _BIT(0)

#define SYSCFG  ((syscfg_reg_t *)T1_SYS_BASE)

#endif /* SYSCTL_H_ */
